1. Field of the Invention
The disclosures herein relate to a current limiting circuit which includes a detection circuit for detecting a detection voltage responsive to an output voltage and a control current generating circuit for generating a control current responsive to the detection voltage thereby to limit an output current in response to the control current, and also relate to a power-supply circuit having such a current limiting circuit.
2. Description of the Related Art
FIG. 3 is a drawing illustrating an example of a related-art power supply circuit. A power supply circuit 10 includes a reference voltage generating circuit 11, a bias circuit 12, a detection circuit 13, a control circuit 14, a current limiting circuit 15, and a current control transistor Q1.
The reference voltage generating circuit 11 and the bias circuit 12 are situated between an input terminal Tin and a ground terminal Tgnd. The detection circuit 13 includes resistors R5 and R6 situated between an output terminal Tout and the ground terminal Tgnd, thereby dividing an output voltage Vout appearing between the output terminal Tout and the ground terminal Tgnd. The voltage resulting from potential division by the resistors R5 and R6 is a voltage responsive to the output voltage Vout. This voltage is supplied to the control circuit 14 as a detection voltage Vs.
The control circuit 14 includes a differential amplifier circuit 21 and a transistor Q2. The non-inverted input node of the differential amplifier circuit 21 receives a reference voltage Vref from the reference voltage generating circuit 11, and the inverted input node of the differential amplifier circuit 21 receives the detection voltage Vs from the detection circuit 13.
The differential amplifier circuit 21 outputs an electric current responsive to a difference between the reference voltage Vref and the detection voltage Vs. The output current of the differential amplifier circuit 21 is supplied to a transistor Q2. The transistor Q2 is an NPN transistor.
The base of the transistor Q2 receives the output of the differential amplifier circuit 21 and the output of the current limiting circuit 15. The collector of the transistor Q2 is connected to the base of the current control transistor Q1 and to the base of a transistor Q3 that is part of the current limiting circuit 15. The emitter of the transistor Q2 is connected to the ground terminal Tgnd, so that the collector current of the transistor Q2 is converted into a voltage (i.e., I-V conversion).
In response to the outputs of the differential amplifier circuit 21 and the current limiting circuit 15, the transistor Q2 controls the potential of the bases of the current control transistor Q1 and the transistor Q3 that is part of the control circuit 14. The transistor Q1 is a PNP transistor. The current control transistor Q1 has the emitter thereof connected to the input terminal Tin, the collector thereof connected to the output terminal Tout, and the base thereof connected to the collector of the transistor Q2. The current control transistor Q1 supplies a current responsive to the collector potential of the transistor Q2 from the input terminal Tin to the output terminal Tout.
The current limiting circuit 15 includes transistors Q3 through Q6 and resistors R1 through R4. The resistors R3 and R4 are connected in series between the output terminal Tout and the ground terminal Tgnd, thereby dividing the output voltage Vout. The voltage obtained by the division is supplied to the base of a transistor Q4.
The transistor Q4 is a PNP transistor. The transistor Q4 has the base thereof connected to the joining point between the resistor R3 and the resistor R4, the emitter thereof coupled via the resistor R2 to the collector of the transistor Q3, and the collector thereof connected to the collector and base of the transistor Q5.
The transistor Q5 is an NPN transistor. The transistor Q5 has the collector thereof connected to the collector of the transistor Q4, the emitter thereof connected to the ground terminal Tgnd, and the base thereof connected to the collector of the transistor Q4 and to the base of the transistor Q6.
The transistor Q6 is an NPN transistor. The transistor Q6 has the collector thereof connected to the base of the transistor Q2, the emitter thereof connected to the ground terminal Tgnd, and the base thereof connected to the base and collector of the transistor Q5. The transistors Q5 and Q6 constitute a current mirror circuit, which pulls from the base of the transistor Q2 a current responsive to the collector current Ic4 of the transistor Q4.
The resistor R1 connects between the collector of the transistor Q3 and the ground terminal Tgnd. The transistor Q3 is a PNP transistor. The transistor Q3 has the emitter thereof connected to the input terminal Tin, the collector thereof connected to the resistors R1 and R2, and the base thereof connected to the collector of the transistor Q2. The transistor Q3 supplies a current responsive to the collector potential of the transistor Q2 to the resistor R1 and the resistor R2. The transistors Q1 and Q3 have such device areas that when the collector current of the current control transistor Q1 is Io, the collector current of the transistor Q3 is equal to Io/n.
In the power supply circuit 10, as the voltage Vt obtained by the I-V conversion of the collector current of the transistor Q3 rises to a threshold voltage of the current limiting circuit 15 that is equal to (R4/(R3+R4))Vout+Vbe4, the transistor Q4 is turned on to activate a current limiting function. Here, Vbe4 is the base-emitter voltage of the transistor Q4.
Upon the activation of the current limiting function, the output voltage Vout drops, resulting in a drop of the voltage (=R4/(R3+R4)Vout) at the joining point between the resistor R3 and the resistor R4. This arrangement is expected to provide current-to-voltage characteristics as illustrated in FIG. 4. FIG. 4 is a drawing illustrating the current-to-voltage characteristics of the related-art power supply circuit.
A power supply circuit that has a current limiting circuit expected to provide the current-to-voltage characteristics illustrated in FIG. 4 is disclosed in Japanese Patent Application Publication No. 2002-304225, for example.
In the related-art power supply circuit described above, a drop of the output voltage Vout to the ground potential results in the base potential of the transistor Q4 being at the ground potential, which places the transistor Q4 in the saturated region. As the transistor Q4 is placed in the saturated region, a parasitic device Q7 as illustrated in FIG. 5 is turned on. FIG. 5 is a drawing illustrating an example of a related-art power supply circuit that includes a parasitic device.
With the parasitic device Q7 being turned on, the current-to-voltage characteristics of the power supply circuit 10 become the characteristics as illustrated in FIG. 6, thereby failing to provide the desired characteristics illustrated in FIG. 4. FIG. 6 is a drawing illustrating the current-to-voltage characteristics of a related-art power supply circuit that includes a parasitic device.
Accordingly, it may be desirable to provide a power supply circuit and a current limiting circuit that can provide desired current-to-voltage characteristics.